As the semiconductor devices keep scaling down in size, three-dimensional multi-gate structures, such as the fin-type field effect transistor (FinFET), have been developed to replace planar Complementary Metal Oxide Semiconductor (CMOS) devices. A structural feature of the FinFET is the silicon-based fin that extends upright from the surface of the substrate, and the gate wrapping around the conducting channel that is formed by the semiconductor fin further provides a better electrical control over the channel.
Currently, the cross-sectional profile of the semiconductor fins in FinFETs may affect the performance of FinFETs enormously. The semiconductor fins may be consumed or damaged by an etching step of shallow trench isolation (STI) process, when the etching condition is too aggressive for the semiconductor fins. Furthermore, in the proximity of the boundary between dense area and isolated area, the cross-sectional profile of the semiconductor fins may be asymmetric or uneven due to loading effect.